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top221-227 topswitch-ii family three-terminal off-line pwm switch figure 1. typical flyback application. easier. the standard 8l pdip package option reduces cost in lower power, high efficiency applications. the internal lead frame of this package uses six of its pins to transfer heat from the chip directly to the board, eliminating the cost of a heat sink. topswitch incorporates all functions necessary for a switched mode control system into a three terminal monolithic ic: power mosfet, pwm controller, high voltage start up circuit, loop compensation and fault protection circuitry. product highlights lowest cost, lowest component count switcher solution cost competitive with linears above 5w very low ac/dc losses up to 90% efficiency built-in auto-restart and current limiting latching thermal shutdown for system level protection implements flyback, forward, boost or buck topology works with primary or opto feedback stable in discontinuous or continuous conduction mode source connected tab for low emi circuit simplicity and design tools reduce time to market description the second generation topswitch-ii family is more cost effective and provides several enhancements over the first generation topswitch family. the topswitch-ii family extends the power range from 100w to 150w for 100/115/230 vac input and from 50w to 90w for 85-265 vac universal input. this brings topswitch technology advantages to many new applications, i.e. tv, monitor, audio amplifiers, etc. many significant circuit enhancements that reduce the sensitivity to board layout and line transients now make the design even pi-1951-091996 ac in d s c control topswitch 6 w 10 w 15 w 20 w top221y top222y top223y top224y top225y top226y top227y 9 w 15 w 25 w 30 w top221p or top221g top222p or top222g top223p or top223g top224p or top224g output power table to-220 (y) package 1 8l pdip (p) or 8l smd (g) package 2 . p max 5,6 part order number single voltage input 100/115/230 vac 15% 3 wide range input 85 to 265 vac single voltage input 100/115/230 vac 15% 3 wide range input 85 to 265 vac p max 5,6 7 w 15 w 30 w 45 w 60 w 75 w 90 w p max 4,6 12 w 25 w 50 w 75 w 100 w 125 w 150 w p max 4,6 notes: 1 . package outline: to-220/3 2 . package outline: dip-8 or smd-8 3. 100/115 vac with doubler input 4 . assumes appropriate heat sinking to keep the maximum topswitch junction temperature below 100 c. 5 . soldered to 1 sq. in.( 6.45 cm 2 ), 2 oz. copper clad (610 gm/m 2 ) 6 . p max is the maximum practical continuous power output level for conditions shown. the continuous power capability in a given application depends on thermal environment, transformer design, efficiency required, minimum specified input voltage , input storage capacitance, etc. 7 . refer to key application considerations section when using topswitch-ii in an existing topswitch design. part order number july 2001
top221-227 d 7/01 2 figure 2. functional block diagram. pin functional description drain pin: output mosfet drain connection. provides internal bias current during start-up operation via an internal switched high- voltage current source. internal current sense point. control pin: error amplifier and feedback current input pin for duty cycle control. internal shunt regulator connection to provide internal bias current during normal operation. it is also used as the connection point for the supply bypass and auto-restart/ compensation capacitor. source pin: y package output mosfet source connection for high voltage power return. primary side circuit common and reference point. p and g package primary side control circuit common and reference point. source (hv rtn) pin: (p and g package only) output mosfet source connection for high voltage power return. pi-1935-091696 shutdown/ auto-restart pwm comparator clock saw oscillator controlled turn-on gate driver internal supply 5.7 v 4.7 v source s r q q d max - + control - + 5.7 v i fb r e z c v c minimum on-time delay + - v i limit leading edge blanking power-up reset s r q q 8 0 1 thermal shutdown shunt regulator/ error amplifier + - drain pi-2084-040401 control drain source y package (to-220/3) tab internally connected to source pin control 8 5 7 6 drain source (hv rtn) source source 1 4 2 3 source (hv rtn) source (hv rtn) source p package (dip-8) g package (smd-8) figure 3. pin configuration.
top221-227 d 7/01 3 topswitch-ii family functional description topswitch is a self biased and protected linear control current- to-duty cycle converter with an open drain output. high efficiency is achieved through the use of cmos and integration of the maximum number of functions possible. cmos process significantly reduces bias currents as compared to bipolar or discrete solutions. integration eliminates external power resistors used for current sensing and/or supplying initial start- up bias current. during normal operation, the duty cycle of the internal output mosfet decreases linearly with increasing control pin current as shown in figure 4. to implement all the required control, bias, and protection functions, the drain and control pins each perform several functions as described below. refer to figure 2 for a block diagram and to figure 6 for timing and voltage waveforms of the topswitch integrated circuit. pi-2040-050197 d max d min duty cycle (%) i c (ma) 2.0 6.0 slope = pwm gain i b i cd1 auto-restart figure 4. relationship of duty cycle to control pin current. drain 0 v in v c 0 4.7 v 5.7 v 8 cycles 95% 5% off switching switching off i c charging c t i cd1 discharging c t i cd2 discharging c t i c charging c t off pi-1956-092496 drain 0 v in v c 0 4.7 v 5.7 v off switching (b) (a) c t is the total external capacitance connected to the control pin figure 5. start-up waveforms for (a) normal operation and (b) auto-restart.
top221-227 d 7/01 4 control voltage supply control pin voltage v c is the supply or bias voltage for the controller and driver circuitry. an external bypass capacitor closely connected between the control and source pins is required to supply the gate drive current. the total amount of capacitance connected to this pin (c t ) also sets the auto- restart timing as well as control loop compensation. v c is regulated in either of two modes of operation. hysteretic regulation is used for initial start-up and overload operation. shunt regulation is used to separate the duty cycle error signal from the control circuit supply current. during start-up, control pin current is supplied from a high-voltage switched current source connected internally between the drain and control pins. the current source provides sufficient current to supply the control circuitry as well as charge the total external capacitance (c t ). the first time v c reaches the upper threshold, the high-voltage current source is turned off and the pwm modulator and output transistor are activated, as shown in figure 5(a). during normal operation (when the output voltage is regulated) feedback control current supplies the v c supply current. the shunt regulator keeps v c at typically 5.7 v by shunting control pin feedback current exceeding the required dc supply current through the pwm error signal sense resistor r e . the low dynamic impedance of this pin (z c ) sets the gain of the error amplifier when used in a primary feedback configuration. the dynamic impedance of the control pin together with the external resistance and capacitance determines the control loop compensation of the power system. if the control pin total external capacitance (c t ) should discharge to the lower threshold, the output mosfet is turned off and the control circuit is placed in a low-current standby mode. the high-voltage current source turns on and charges the external capacitance again. charging current is shown with a negative polarity and discharging current is shown with a positive polarity in figure 6. the hysteretic auto-restart comparator keeps v c within a window of typically 4.7 to 5.7 v by turning the high-voltage current source on and off as shown in figure 5(b). the auto-restart circuit has a divide-by-8 counter which prevents the output mosfet from turning on again until eight discharge-charge cycles have elapsed. the counter effectively limits topswitch power dissipation by reducing the auto-restart duty cycle to typically 5%. auto- restart continues to cycle until output voltage regulation is again achieved. bandgap reference all critical topswitch internal voltages are derived from a temperature-compensated bandgap reference. this reference is also used to generate a temperature-compensated current source which is trimmed to accurately set the oscillator frequency and mosfet gate drive current. oscillator the internal oscillator linearly charges and discharges the internal capacitance between two voltage levels to create a sawtooth waveform for the pulse width modulator. the oscillator sets the pulse width modulator/current limit latch at the beginning of each cycle. the nominal frequency of 100 khz was chosen to minimize emi and maximize efficiency in power supply applications. trimming of the current reference improves the frequency accuracy. pulse width modulator the pulse width modulator implements a voltage-mode control loop by driving the output mosfet with a duty cycle inversely proportional to the current into the control pin which generates a voltage error signal across r e . the error signal across r e is filtered by an rc network with a typical corner frequency of 7 khz to reduce the effect of switching noise. the filtered error signal is compared with the internal oscillator sawtooth waveform to generate the duty cycle waveform. as the control current increases, the duty cycle decreases. a clock signal from the oscillator sets a latch which turns on the output mosfet. the pulse width modulator resets the latch, turning off the output mosfet. the maximum duty cycle is set by the symmetry of the internal oscillator. the modulator has a minimum on-time to keep the current consumption of the topswitch independent of the error signal. note that a minimum current must be driven into the control pin before the duty cycle begins to change. gate driver the gate driver is designed to turn the output mosfet on at a controlled rate to minimize common-mode emi. the gate drive current is trimmed for improved accuracy. error amplifier the shunt regulator can also perform the function of an error amplifier in primary feedback applications. the shunt regulator voltage is accurately derived from the temperature compensated bandgap reference. the gain of the error amplifier is set by the control pin dynamic impedance. the control pin clamps external circuit signals to the v c voltage level. the control pin current in excess of the supply current is separated by the shunt regulator and flows through r e as a voltage error signal. cycle-by-cycle current limit the cycle by cycle peak drain current limit circuit uses the output mosfet on-resistance as a sense resistor. a current limit comparator compares the output mosfet on-state drain- source voltage, v ds(on) with a threshold voltage. high drain current causes v ds(on) to exceed the threshold voltage and turns the output mosfet off until the start of the next clock cycle. the current limit comparator threshold voltage is temperature topswitch-ii family functional description (cont.)
top221-227 d 7/01 5 pi-2030-042397 v in v out 0 i out 0 1 2 1 3 1 drain 0 v in v c 0 ? ? ?? ? ? 12 12 81 0 i c ? ? ?? ? ? 12 8 812 81 v c(reset) compensated to minimize variation of the effective peak current limit due to temperature related changes in output mosfet r ds(on) . the leading edge blanking circuit inhibits the current limit comparator for a short time after the output mosfet is turned on. the leading edge blanking time has been set so that current spikes caused by primary-side capacitances and secondary-side rectifier reverse recovery time will not cause premature termination of the switching pulse. the current limit can be lower for a short period after the leading edge blanking time as shown in figure 12. this is due to dynamic characteristics of the mosfet. to avoid triggering the current limit in normal operation, the drain current waveform should stay within the envelope shown. shutdown/auto-restart to minimize topswitch power dissipation, the shutdown/ auto-restart circuit turns the power supply on and off at an auto- restart duty cycle of typically 5% if an out of regulation condition persists. loss of regulation interrupts the external current into the control pin. v c regulation changes from shunt mode to the hysteretic auto-restart mode described above. when the fault condition is removed, the power supply output becomes regulated, v c regulation returns to shunt mode, and normal operation of the power supply resumes. overtemperature protection temperature protection is provided by a precision analog circuit that turns the output mosfet off when the junction temperature exceeds the thermal shutdown temperature (typically 135 c). activating the power-up reset circuit by removing and restoring input power or momentarily pulling the control pin below the power-up reset threshold resets the latch and allows topswitch to resume normal power supply operation. v c is regulated in hysteretic mode and a 4.7 v to 5.7 v (typical) sawtooth waveform is present on the control pin when the power supply is latched off. high-voltage bias current source this current source biases topswitch from the drain pin and charges the control pin external capacitance (c t ) during start-up or hysteretic operation. hysteretic operation occurs during auto-restart and overtemperature latched shutdown. the current source is switched on and off with an effective duty cycle of approximately 35%. this duty cycle is determined by the ratio of control pin charge (i c ) and discharge currents (i cd1 and i cd2 ). this current source is turned off during normal operation when the output mosfet is switching. figure 6. typical waveforms for (1) normal operation, (2) auto-restart, and (3) power down reset.
top221-227 d 7/01 6 figure 7. schematic diagram of a 4 w topswitch-ii standby power supply using an 8 lead pdip. application examples following are just two of the many possible topswitch implementations. refer to the data book and design guide for additional examples. 4 w standby supply using 8 lead pdip figure 7 shows a 4 w standby supply. this supply is used in appliances where certain standby functions (e.g. real time clock, remote control port) must be kept active even while the main power supply is turned off. the 5 v secondary is used to supply the standby function and the 12 v non-isolated output is used to supply power for the pwm controller of the main power supply and other primary side functions. for this application the input rectifiers and input filter are sized for the main supply and are not shown. the input dc rail may vary from 100 v to 380 v dc which corresponds to the full universal ac input range. the top221 is packaged in an 8 pin power dip package. the output voltage (5 v) is directly sensed by the zener diode (vr1) and the optocoupler (u2). the output voltage is determined by the sum of the zener voltage and the voltage drop across the led of the optocoupler (the voltage drop across r1 is negligible). the output transistor of the optocoupler drives the control pin of the top221. c5 bypasses the control pin and provides control loop compensation and sets the auto-restart frequency. the transformer s leakage inductance voltage spikes are snubbed by r3 and c1 through diode d1. the bias winding is rectified and filtered by d3 and c4 providing a non-isolated 12 v output which is also used to bias the collector of the optocoupler s output transistor. the isolated 5 v output winding is rectified by d2 and filtered by c2, l1 and c3. wide-range dc input d s c control pi-2115-040401 + - r3 47 k ? d1 uf4005 c1 2.2 nf 1 kv d2 uf5401 top221p l1 3.3 h d3 1n4148 c4 100 f 16 v u2 pc817a r1 10 ? c3 100 f 10 v +5 v c5 47 f 10 v c2 330 f 10 v u1 r2 100 ? vr1 topswitch-ii t1 rtn + - 12 v non-isolated
top221-227 d 7/01 7 20 w universal supply using 8 lead pdip figure 8 shows a 12 v, 20 w secondary regulated flyback power supply using the top224p in an eight lead pdip package and operating from universal 85 to 265 vac input voltage. this example demonstrates the advantage of the higher power 8 pin leadframe used with the topswitch-ii family. this low cost package transfers heat directly to the board through six source pins, eliminating the heatsink and the associated cost. efficiency is typically 80% at low line input. output voltage is directly sensed by optocoupler u2 and zener diode vr2. the output voltage is determined by the zener diode (vr2) voltage and the voltage drops across the optocoupler (u2) led and resistor r1. other output voltages are possible by adjusting the transformer turns ratio and value of zener diode vr2. ac power is rectified and filtered by br1 and c1 to create the high voltage dc bus applied to the primary winding of t1. the other side of the transformer primary is driven by the integrated topswitch-ii high-voltage mosfet. d1 and vr1 clamp leading-edge voltage spikes caused by transformer leakage inductance. the power secondary winding is rectified and filtered by d2, c2, l1, and c3 to create the 12 v output voltage. r2 and vr2 provide a slight pre-load on the 12 v output to improve load regulation at light loads. the bias winding is rectified and filtered by d3 and c4 to create a topswitch bias voltage. l2 and y1-safety capacitor c7 attenuate common mode emission currents caused by high voltage switching waveforms on the drain side of the primary winding and the primary to secondary capacitance. leakage inductance of l2 with c1 and c6 attenuates differential-mode emission currents caused by the fundamental and harmonics of the trapezoidal or triangular primary current waveform. c5 filters internal mosfet gate drive charge current spikes on the control pin, determines the auto-restart frequency, and together with r1 and r3, compensates the control loop. figure 8. schematic diagram of a 20 w universal input topswitch-ii power supply using an 8 lead pdip. pi-2019-033197 d2 mur420 d3 1n4148 c2 330 f 35 v c3 220 f 35 v t1 d1 byv26c vr1 p6ke200 vr2 1n5241b 11 v r2 220 ? br1 400 v c1 47 f 400 v f1 3.15 a j1 c6 0.1 f 250 vac l2 22 mh l n c5 47 f u1 top224p d s c control topswitch-ii r3 6.8 ? l1 3.3 h c4 0.1 f u2 pc817a r1 100 ? c7 1 nf 250 vac y1 +12 v rtn
top221-227 d 7/01 8 key application considerations general guidelines keep the source pin length very short. use a kelvin connection to the source pin for the control pin bypass capacitor. use single point grounding techniques at the source pin as shown in figure 9. minimize peak voltage and ringing on the drain voltage at turn-off. use a zener or tvs zener diode to clamp the drain voltage below the breakdown voltage rating of topswitch under all conditions, including start-up and overload. the maximum recommended clamp zener voltage for the top2xx series is 200 v and the corresponding maximum reflected output voltage on the primary is 135 v. please see step 4: an-16 in the 1996-97 data book and design guide or on our web site. the transformer should be designed such that the rate of change of drain current due to transformer saturation is within the absolute maximum specification ( ? i d in 100 ns before turn off as shown in figure 13). as a guideline, for most common transformer cores, this can be achieved by maintaining the peak flux density (at maximum i limit current) below 4200 gauss (420 mt). the transformer spreadsheets rev. 2.1 (or later) for continuous and rev.1.0 (or later) for discontinuous conduction mode provide the necessary information. do not plug topswitch into a hot ic socket during test. external control pin capacitance may be charged to excessive voltage and cause topswitch damage. while performing topswitch device tests, do not exceed maximum control pin voltage of 9 v or maximum control pin current of 100 ma. under some conditions, externally provided bias or supply current driven into the control pin can hold the topswitch in one of the 8 auto-restart cycles indefinitely and prevent starting. to avoid this problem when doing bench evaluations, it is recommended that the v c power supply be turned on before the drain voltage is applied. topswitch can also be reset by shorting the control pin to the source pin momentarily. control pin currents during auto-restart operation are much lower at low input voltages (< 36 v) which increases the auto-restart cycle time (see the i c vs. drain voltage characteristic curve). short interruptions of ac power may cause topswitch to enter the 8-count auto-restart cycle before starting again. this is because the input energy storage capacitors are not completely discharged and the control pin capacitance has not discharged below the internal power-up reset voltage. in some cases, minimum loading may be necessary to keep a lightly loaded or unloaded output voltage within the desired range due to the minimum on-time. replacing topswitch with topswitch-ii there is no external latching shutdown function in topswitch-ii. otherwise, the functionality of the topswitch-ii devices is same as that of the topswitch family. however, before considering topswitch-ii as a 'drop in' replacement in an existing topswitch design, the design should be verified as described below. the new topswitch-ii family offers more power capability than the original topswitch family for the same mosfet r ds(on) . therefore, the original topswitch design must be reviewed to make sure that the selected topswitch-ii replacement device and other primary components are not over stressed under abnormal conditions. the following verification steps are recommended: check the transformer design to make sure that it meets the ? i d specification as outlined in the general guidelines section above. thermal: higher power capability of the topswitch-ii would in many instances allow use of a smaller mosfet device (higher r ds(on) ) for reduced cost. this may affect topswitch power dissipation and power supply efficiency. therefore thermal performance of the power supply must be verified with the selected topswitch-ii device . clamp voltage: reflected and clamp voltages should be verified not to exceed recommended maximums for the top2xx series: 135 v reflected/200 v clamp. please see step 4: an-16 in the data book and design guide and readme.txt file attached to the transformer design spreadsheets. agency approval: migrating to topswitch-ii may require agency re-approval.
top221-227 d 7/01 9 figure 9. recommended topswitch layout. pi-2021-041798 pc board kelvin-connected auto-restart/bypass capacitor c5 and/or compensation network bias/feedback input bias/feedback return high-voltage return bend drain pin forward if needed for creepage. drain source control do not bend source pin. keep it short. high voltage return bias/feedback return d s c bias/feedback input control source source drain top view high voltage return bias/feedback return bias/feedback input dip-8/smd-8 package to-220 package top view c5 kelvin-connected auto-restart/bypass capacitor c5 and/or compensation network kelvin-connected auto-restart/bypass capacitor c5 and/or compensation network c5 c5 design tools the following tools available from power integrations greatly simplify topswitch based power supply design. data book and design guide includes extensive application information excel spreadsheets for transformer design - use of this tool is strongly recommended for all topswitch designs. reference design boards production viable designs that are assembled and tested. all data sheets, application literature and up-to-date versions of the transformer design spreadsheets can be downloaded from our web site at www.powerint.com . a diskette of the transformer design spreadsheets may also be obtained by sending in the completed form provided at the end of this data sheet.
top221-227 d 7/01 10 absolute maximum ratings (1) drain voltage ............................................ -0.3 to 700 v drain current increase ( ? i d ) in 100 ns except during blanking time ......................................... 0.1 x i limit(max) (2) control voltage ..................................... - 0.3 v to 9 v control current ............................................... 100 ma storage temperature ..................................... -65 to 150 c notes: 1. all voltages referenced to source, t a = 25 c. 2. related to transformer saturation see figure 13. 3. normally limited by internal circuitry. 4. 1/16" from case for 5 seconds. operating junction temperature (3) ................ -40 to 150 c lead temperature (4) ................................................ 260 c thermal impedance: y package ( ja ) (5) .................70 c/w ( jc ) (6) ...................2 c/w p/g package: ( ja ) .........45 c/w (7) ; 35 c/w (8) ( jc ) (6) ...............................11 c/w 5. free standing with no heatsink. 6. measured at tab closest to plastic interface or source pin. 7. soldered to 0.36 sq. inch (232 mm 2 ), 2 oz. (610 gm/m 2 ) copper clad. 8. soldered to 1 sq. inch (645 mm 2 ), 2 oz. (610 gm/m 2 ) copper clad. 90 100 110 64 67 70 0.7 1.7 2.7 -21 -16 -11 -0.05 0.8 2.0 3.3 10 15 22 0.18 -2.4 -1.9 -1.2 -2 -1.5 -0.8 0.4 f osc d max d min i b z c i c control functions output frequency maximum duty cycle minimum duty cycle pwm gain pwm gain temperature drift external bias current dynamic impedance dynamic impedance temperature drift control pin charging current charging current temperature drift khz % % %/ma %/ma/ c ma ? %/ c ma %/ c shutdown/auto-restart conditions (unless otherwise specified) see figure 14 source = 0 v ; t j = -40 to 125 c min typ max parameter symbol units i c = 4 ma, t j = 25 c i c = i cd1 + 0.4 ma, see figure 10 i c = 10 ma, see figure 10 i c = 4 ma, t j = 25 c see figure 4 see note a see figure 4 i c = 4 ma, t j = 25 c see figure 11 v c = 0 v t j = 25 c v c = 5 v see note a
top221-227 d 7/01 11 5.7 4.4 4.7 5.0 0.6 1.0 259 258 1.2 0.23 0.25 0.28 0.45 0.50 0.55 0.90 1.00 1.10 1.35 1.50 1.65 1.80 2.00 2.20 2.25 2.50 2.75 2.70 3.00 3.30 0.75 x i limit(min) 180 v c(ar) i limit i init t leb shutdown/auto-restart (cont.) auto-restart threshold voltage uv lockout threshold voltage auto-restart hysteresis voltage auto-restart duty cycle auto-restart frequency self-protection current limit initial current limit leading edge blanking time circuit protection v v v % hz a a ns 85 vac (rectified line input) 265 vac (rectified line input) 0.6 x i limit(min) conditions (unless otherwise specified) see figure 14 source = 0 v ; t j = -40 to 125 c min typ max parameter symbol units top221-222 top223-227 s1 open s1 open s1 open s1 open s1 open di/dt = 40 ma/ s, top221y t j = 25 c top221p or g di/dt = 80 ma/ s, top222y t j = 25 c top222p or g di/dt = 160 ma/ s, top223y t j = 25 c top223p or g di/dt = 240 ma/ s, top224y t j = 25 c top224p or g di/dt = 320 ma/ s, top225y t j = 25 c di/dt = 400 ma/ s, top226y t j = 25 c di/dt = 480 ma/ s, top227y t j = 25 c see figure 12 t j = 25 c i c = 4 ma, t j = 25 c
top221-227 d 7/01 12 t ild v c(reset) r ds(on) i dss bv dss t r t f 100 125 135 2.0 3.3 4.3 31.2 36.0 51.4 60.0 15.6 18.0 25.7 30.0 7.8 9.0 12.9 15.0 5.2 6.0 8.6 10.0 3.9 4.5 6.4 7.5 3.1 3.6 5.2 6.0 2.6 3.0 4.3 5.0 250 700 100 50 current limit delay thermal shutdown temperature power-up reset threshold voltage on-state resistance off-state current breakdown voltage rise time fall time ns c v ? a v ns ns circuit protection (cont.) output conditions (unless otherwise specified) see figure 14 source = 0 v ; t j = -40 to 125 c min typ max parameter symbol units i c = 4 ma i c = 4 ma s2 open top221 t j = 25 c i d = 25 ma t j = 100 c top222 t j = 25 c i d = 50 ma t j = 100 c top223 t j = 25 c i d = 100 ma t j = 100 c top224 t j = 25 c i d = 150 ma t j = 100 c top225 t j = 25 c i d = 200 ma t j = 100 c top226 t j = 25 c i d = 250 ma t j = 100 c top227 t j = 25 c i d = 300 ma t j = 100 c see note b v ds = 560 v, t a = 125 c see note b i d = 100 a, t a = 25 c measured in a typical flyback converter application.
top221-227 d 7/01 13 v c(shunt) i cd1 i cd2 36 5.5 5.7 6.0 50 0.6 1.2 1.6 0.7 1.4 1.8 0.5 0.8 1.1 drain supply voltage shunt regulator voltage shunt regulator temperature drift control supply/ discharge current v v ppm/ c ma output (cont.) notes: a. for specifications with negative values, a negative temperature coefficient corresponds to an increase in magnitude with increasing temperature, and a positive temperature coefficient corresponds to a decrease in magnitude with increasing temperature. b. the breakdown voltage and leakage current measurements can be accomplished as shown in figure 15 by using the following sequence: i. the curve tracer should initially be set at 0 v. the base output should be adjusted through a voltage sequence of 0 v, 6.5 v, 4.3 v, and 6.5 v, as shown. the base current from the curve tracer should not exceed 100 ma. this control pin sequence interrupts the auto-restart sequence and locks the topswitch internal mosfet in the off state. ii. the breakdown and the leakage measurements can now be taken with the curve tracer. the maximum voltage from the curve tracer must be limited to 700 v under all conditions. c. it is possible to start up and operate topswitch at drain voltages well below 36 v. however, the control pin charging current is reduced, which affects start-up time, auto-restart frequency, and auto-restart duty cycle. refer to the characteristic graph on control pin charge current (i c ) vs. drain voltage for low voltage operation characteristics. conditions (unless otherwise specified) see figure 14 source = 0 v ; t j = -40 to 125 c min typ max parameter symbol units see note c i c = 4 ma output top221-224 mosfet enabled top225-227 output mosfet disabled
top221-227 d 7/01 14 figure 11. topswitch control pin i-v characteristic. figure 10. topswitch duty cycle measurement. figure 12. self-protection current limit envelope. pi-2031-040401 ? i d 100 ns t leb drain current 0 a figure 13. example of ? i d on drain current waveform with saturated transformer. 0.8 1.3 1.2 1.1 0.9 0.8 1.0 0 012 6 8 3 time ( s) drain current (normalized) pi-2022-033001 45 7 0.7 0.6 0.5 0.4 0.3 0.2 0.1 i limit(max) @ 25 c i limit(min) @ 25 c i init(min) @ 85 vac i init(min) @ 265 vac t leb (blanking time) pi-2039-040401 drain voltage hv 0 v 90% 10% 90% t 2 t 1 d = t 1 t 2 120 100 80 40 20 60 0 0246810 control pin voltage (v) control pin current (ma) pi-1939-091996 1 slope dynamic impedance =
top221-227 d 7/01 15 pi-1964-110696 0.1 f 47 f 0-50 v 40 v 470 ? 5 w s2 s1 470 ? notes: 1. this test circuit is not applicable for current limit or output characteristic measurements. 2. for p package, short all source and source (hv rtn) pins together. d s c control topswitch figure 14. topswitch general test circuit. figure 15. breakdown voltage and leakage current measurement test circuit. pi-2109-040401 curve tracer note: this control pin sequence interrupts the auto-restart sequence and locks the topswitch internal mosfet in the off state. d s c control topswitch b c e 6.5 v 4.3 v
top221-227 d 7/01 16 the following precautions should be followed when testing topswitch by itself outside of a power supply. the schematic shown in figure 14 is suggested for laboratory testing of topswitch . when the drain supply is turned on, the part will be in the auto-restart mode. the control pin voltage will be oscillating at a low frequency from 4.7 to 5.7 v and the drain is turned on every eighth cycle of the control pin oscillation. if the control pin power supply is turned on while in this bench test precautions for evaluation of electrical characteristics typical performance characteristics auto-restart mode, there is only a 12.5% chance that the control pin oscillation will be in the correct state (drain active state) so that the continuous drain voltage waveform may be observed. it is recommended that the v c power supply be turned on first and the drain power supply second if continuous drain voltage waveforms are to be observed. the 12.5% chance of being in the correct state is due to the 8:1 counter. temporarily shorting the control pin to the source pin will reset topswitch, which then will come up in the correct state. 2 1.2 1.6 0 0 20 40 60 80 100 drain voltage (v) control pin charging current (ma) i c vs. drain voltage pi-1145-103194 0.4 0.8 v c = 5 v 1.1 1.0 0.9 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) breakdown voltage (v) (normalized to 25 c) breakdown vs. temperature pi-176b-051391 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) current limit vs. temperature pi-1125-033001 current limit (normalized to 25 c) 1.2 1.0 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 junction temperature ( c) frequency vs. temperature pi-1123a-033001 output frequency (normalized to 25 c)
top221-227 d 7/01 17 typical performance characteristics (cont.) 3 0 0 246810 drain voltage (v) drain current (a) output characteristics pi-1940-033001 1 tcase=25 c tcase=100 c 2 top227 1.00 top226 0.83 top225 0.67 top224 0.50 top223 0.33 top222 0.17 top221 0.09 scaling factors: 1000 10 0 400 200 600 drain voltage (v) drain capacitance (pf) c oss vs. drain voltage 100 pi-1941-033001 top227 1.00 top226 0.83 top225 0.67 top224 0.50 top223 0.33 top222 0.17 top221 0.09 scaling factors: 500 300 400 100 200 0 0 200 400 600 drain voltage (v) power (mw) drain capacitance power pi-1942-033001 top227 1.00 top226 0.83 top225 0.67 top224 0.50 top223 0.33 top222 0.17 top221 0.09 scaling factors:
top221-227 d 7/01 18 b k f g c j l m e a d dim a b c d e f g h j k l m n o p pi-1848-040901 inches .460-.480 .400-.415 .236-.260 .240 - ref. .520-.560 .028-.038 .045-.055 .090-.110 .165-.185 .045-.055 .095-.115 .015-.020 .705-.715 .146-.156 .103-.113 mm 11.68-12.19 10.16-10.54 5.99-6.60 6.10 - ref. 13.21-14.22 .71-.97 1.14-1.40 2.29-2.79 4.19-4.70 1.14-1.40 2.41-2.92 .38-.51 17.91-18.16 3.71-3.96 2.62-2.87 h n o p notes: 1. package dimensions conform to jedec specification to-220 ab for standard flange mounted, peripheral lead package; .100 inch lead spacing (plastic) 3 leads (issue j, march 1987) 2. controlling dimensions are inches. 3. pin numbers start with pin 1, and continue from left to right when viewed from the top. 4. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15 mm) on any side. 5. position of terminals to be measured at a position .25 (6.35 mm) from the body. 6. all terminals are solder plated. y03a to-220/3 pi-2076-040901 1 a k j1 4 l g 85 c n p08a dip-8 d s .004 (.10) j2 -e- -d- b -f- dim a b c g h j1 j2 k l m n p q inches 0.370-0.385 0.245-0.255 0.125-0.135 0.015-0.040 0.120-0.135 0.060 (nom) 0.014-0.022 0.010-0.012 0.090-0.110 0.030 (min) 0.300-0.320 0.300-0.390 0.300 bsc mm 9.40-9.78 6.22-6.48 3.18-3.43 0.38-1.02 3.05-3.43 1.52 (nom) 0.36-0.56 0.25-0.30 2.29-2.79 0.76 (min) 7.62-8.13 7.62-9.91 7.62 bsc notes: 1. package dimensions conform to jedec specification ms-001-ab for standard dual in-line (dip) package .300 inch row spacing (plastic) 8 leads (issue b, 7/85).. 2. controlling dimensions are inches. 3. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 4. d, e and f are reference datums on the molded body. h m p q
top221-227 d 7/01 19 pi-2077-042601 1 a j1 4 l 85 c g08a smd-8 d s .004 (.10) j2 e s .010 (.25) -e- -d- b -f- m j3 dim a b c g h j1 j2 j3 j4 k l m p inches 0.370-0.385 0.245-0.255 0.125-0.135 0.004-0.012 0.036-0.044 0.060 (nom) 0.048-0.053 0.032-0.037 0.007-0.011 0.010-0.012 0.100 bsc 0.030 (min) 0.372-0.388 0-8 mm 9.40-9.78 6.22-6.48 3.18-3.43 0.10-0.30 0.91-1.12 1.52 (nom) 1.22-1.35 0.81-0.94 0.18-0.28 0.25-0.30 2.54 bsc 0.76 (min) 9.45-9.86 0-8 notes: 1. package dimensions conform to jedec specification ms-001-ab (issue b, 7/85) except for lead shape and size. 2. controlling dimensions are inches. 3. dimensions shown do not include mold flash or other protrusions. mold flash or protrusions shall not exceed .006 (.15) on any side. 4. d, e and f are reference datums on the molded body. k g h .004 (.10) j4 p .010 (.25) m a s heat sink is 2 oz. copper as big as possible .420 .046 .060 .060 .046 .080 pin 1 .086 .186 .286 solder pad dimensions
top221-227 d 7/01 20 notes - 1) updated package references. 2) corrected spelling. 3) corrected storage temperature jc and updated nomenclature in parameter table. 4) added g package references to self-protection current limit parameter. 5) corrected font sizes in figures. date 12/97 7/01 revision c d korea power integrations international holdings, inc. rm# 402, handuk building 649-4 yeoksam-dong, kangnam-gu, seoul, korea phone: +82-2-568-7520 fax: +82-2-568-7474 e-mail: koreasales@powerint.com world headquarters americas power integrations, inc. 5245 hellyer avenue san jose, ca 95138 usa main: +1 408-414-9200 customer service: phone: +1 408-414-9665 fax: +1 408-414-9765 e-mail: usasales@powerint.com for the latest updates, visit our web site: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein, nor does it convey any license under its patent rights or the rights of others. the pi logo, topswitch , tinyswitch and ecosmart are registered trademarks of power integrations, inc. ?copyright 2001, power integrations, inc. japan power integrations, k.k. keihin-tatemono 1st bldg. 12-20 shin-yokohama 2-chome kohoku-ku, yokohama-shi kanagawa 222-0033, japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com taiwan power integrations international holdings, inc. 17f-3, no. 510 chung hsiao e. rd., sec. 5, taipei, taiwan 110, r.o.c. phone: +886-2-2727-1221 fax: +886-2-2727-1223 e-mail: taiwansales@powerint.com europe & africa power integrations (europe) ltd. centennial court easthampstead road bracknell berkshire, rg12 1yq united kingdom phone: +44-1344-462-300 fax: +44-1344-311-732 e-mail: eurosales@powerint.com china power integrations international holdings, inc. rm# 1705, bao hua bldg. 1016 hua qiang bei lu shenzhen, guangdong 518031 china phone: +86-755-367-5143 fax: +86-755-377-9610 e-mail: chinasales@powerint.com india (technical support) innovatech #1, 8th main road vasanthnagar bangalore, india 560052 phone: +91-80-226-6023 fax: +91-80-228-9727 e-mail: indiasales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760
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